Feature dimensions in advanced interconnects approach 20 nm and below, and therefore the precise alignment of adjacent metallization layers connected by vias becomes critical for the reliability of Ultra Large Scale Integration (ULSI) devices. One of the key issues of via pitch down-scaling is the increasing impact of the overlay error defined by the lithography step. Since the required overlay down-scaling presents a great challenge by itself, alleviation of this requirement should be done by revising the present patterning schemes.
Overlay error down-scaling is rather slow and does not meet the tolerance for the quickly shrinking via dimensions which creates reliability concerns for the correct via placement. While there are several self-aligned schemes proposed, involving area-selective deposition processes via atomic layer deposition (ALD), one of the key issues in such schemes is that so far there are no defined approaches for selective deposition of low-k dielectric films (k-value below 3.9—that of silicon oxide). Therefore the DoD (dielectric on dielectric) selective deposition is typically done employing high-k dielectrics such as ALD AlOx, HfOx, ZrOx, etc. These dielectrics have k-values above 9 which increases the overall RC-delay of interconnects upon their integration in the metallization layers as inter-metal dielectrics at the via level. Additionally, the finite selectivity of the area-selective deposition ALD processes results in formation of defects such as nucleation of dielectric phase on top of metal lines. This limits the thickness of the ALD dielectric which can be grown selectively (selectivity window) while the presence of defects may induce increased resistance of via contacts.
There is therefore a need for methods of forming a low-k dielectric structure selectively on exposed dielectric locations in a substrate and for substrate structures having dielectric regions covered with a low-k dielectric film and for semiconductor devices comprising such structures.